1. Field of the Invention
This invention relates generally to a junction gated field effect transistor (sometimes referred to as a junction field effect transistor), and more particularly to a junction gated field effect transistor in which a current flowing longitudinally therethrough is controlled laterally.
2. Description of the Prior Art Recently, a field effect power transistor with a triode characteristic has been proposed as a junction gated field effect transistor. See "Denshi Zairyo" (Electric Parts and Materials), October 1971, pages 22 to 27. Such an arrangement is shown as an example of the prior art in FIG. 1 of the drawings hereof. In this prior art structure, a field effect transistor for electric power comprises a P-type semiconductor layer 2 of high impurity concentration, and provides a gate region of a mesh type (in plan view) formed by diffusion into an N-type silicon body 1 of low impurity concentration or even of intrinsic material. This semiconductor body 1 becomes the drain region, while a source region 3 is formed by epitaxial growth on the drain region to surround the P-type semiconductor layer 2. Electrodes 4, 5 and 6 are provided as connections to the drain region 1, the gate region 2 and the source region 3, respectively. This type of field effect transistor has a triode characteristic instead of a saturation characteristic due to the fact that a series resistance from the source to the channel surrounded by the gate is reduced a great deal and a characteristic is obtained wherein the conversion conductance is great at low output impedance due to a gate of mesh type and it is operable at high electric power. With such a prior art junction type field effect transistor, the source region 3 must be formed by epitaxial growth at low temperature and, due to the fact that the gate region 2 of high impurity concentration is adjacent to the source region of high impurity concentration, it is difficult to establish a sufficiently high withstanding voltage therebetween. Furthermore, it is difficult to form the source region 3 with a sufficiently high impurity concentration.
In order to avoid such drawbacks encountered in the transistor shown in FIG. 1, a transistor, as shown in FIG. 2, has been suggested in which a source region 3 is formed to have an N-type region 7 of low impurity concentration in the vicinity of a gate region 2 and an N-type region 8 of high impurity concentration is formed on the region 7 to thereby improve the withstanding voltage. However, with such a transistor, a new drawback may be introduced, namely, the series resistance from the source to the gate or the source resistance increases.
Further, with the transistor shown in FIG. 1, it is rather difficult to form the gate electrode 5, and the gate region 2 and the drain region 1 inevitably become to a mesa type.